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Data Sheet No. PD60198-C
IR2166(S)
PFC & BALLAST CONTROL IC
Features
* PFC, Ballast control and half-bridge driver in one IC * Critical conduction mode boost type PFC * No PFC current sense resistor required * Programmable preheat frequency * Programmable preheat time * Programmable run frequency * Programmable over-current protection * Programmable end-of-life protection * Programmable dead time * Internal ignition ramp * Internal fault counter * DC bus under-voltage reset * Shutdown pin with hysteresis * Internal 15.6V zener clamp diode on Vcc * Micropower startup (150A) * Latch immunity and ESD protection
Description
The IR2166 is a fully integrated, fully protected 600V ballast control IC designed to drive all types of fluorescent lamps. PFC circuitry operates in critical conduction mode and provides for high PF, low THD and DC Bus regulation. The IR2166 features include programmable preheat and run frequencies, programmable preheat time, programmable dead-time, programmable over-current protection, and programmable endof-life protection. Comprehensive protection features such as protection from failure of a lamp to strike, filament failures, end-of-life protection, DC bus undervoltage reset as well as an automatic restart function, have been included in the design. The IR2166 is available in both 16-lead PDIP and 16-lead (narrow body) SOIC packages.
Packages
16-Lead SOIC (narrow body)
16-Lead PDIP
IR2166 Application Diagram
D BUS
+ Rectified AC Line
R BUS R SUPPLY
C VDC
VBUS HO
R GHS M1 C BLOCK LRES C BOOT D BOOT C SNUB D CP1 R5 R6 D CP2 R7 CRES
1 R VDC C BUS
CPH
16
VS
2
15
VB
+
C PH
RT
RT
3
14
IR2166
RPH
VCC
CT CCOMP DZCOMP M3
RPH
+
4
CT
13
COM
CVCC1
CVCC2 R GLS M2 R2 D1 R4 RCS R3
5
COMP
12
LO
6 7 R1
ZX
11
CS
7
PFC
10
SD/EOL
8 R GPFC
9
C SD1
C CS
C SD2
D2
D3
C EOL
R8
- Rectified AC Line
*Please note that this data sheet contains advanced information that could change before the product is released to production.
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IR2166
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM, all currents are defined positive into any lead. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions.
Symbol
VB VS VHO VLO VPFC IOMAX V BUS VCT I CPH I RPH V RPH IRT VRT VCS I CS ISD/EOL I CC IZX ICOMP dV/dt PD RthJA TJ TS TL
Definition
High side floating supply voltage High side floating supply offset voltage High side floating output voltage Low side output voltage PFC gate driver output voltage Maximum allowable output current (HO, LO, PFC) due to external power transistor miller effect VBUS pin voltage CT pin voltage CPH pin current RPH pin current RPH pin voltage RT pin current RT pin voltage Current sense pin voltage Current sense pin current Shutdown pin current Supply current (Note 1) PFC inductor current, zero crossing detection input current PFC error compensation current Allowable offset voltage slew rate Package power dissipation @ TA +25C PD = (TJMAX-TA)/RthJA Thermal resistance, junction to ambient Junction temperature Storage temperature Lead temperature (soldering, 10 seconds) (16-Pin PDIP) (16-Pin SOIC) (16-Pin PDIP) (16-Pin SOIC)
Min.
-0.3 VB - 25 VS - 0.3 -0.3 -0.3 -500 -0.3 -0.3 -5 -5 -0.3 -5 -0.3 -0.3 -5 -5 -20 -5 -5 -50 -- -- -- -- -55 -55 --
Max.
625 VB + 0.3 VB + 0.3 VCC + 0.3 VCC + 0.3 500 VCC + 0.3 VCC + 0.3 5 5 VCC + 0.3 5 VCC + 0.3 5.5 5 5 20 5 5 50 1.80 1.40 70 86 150 150 300
Units
V
mA
V mA V mA V
mA
V/ns W
o
C/W
o
C
Note 1:
This IC contains a zener clamp structure between the chip VCC and COM which has a nominal breakdown voltage of 15.6V. Please note that this supply pin should not be driven by a DC, low impedance power source greater than the VCLAMP specified in the Electrical Characteristics section.
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IR2166
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions.
Symbol
VBS VS V CC I CC CT ISD/EOL I CS IZX TJ Note 2:
Definition
High side floating supply voltage Steady state high side floating supply offset voltage Supply voltage Supply current CT lead capacitance End-of-life lead current Current sense lead current Zero crossing detection pin current Junction temperature
Min.
VCC - 0.7 -1 V CCUV+ Note 2 220 -1 -1 -1 -25
Max.
V CLAMP 600 V CLAMP 10
Units
V
mA
--
1 1 1 125
pF
mA
o
C
Enough current should be supplied into the VCC lead to keep the internal 15.6V zener clamp diode on this lead regulating its voltage, VCLAMP.
Electrical Characteristics
VCC = VBS = VBIAS = 14V +/- 0.25V, VBUS = Open, RT = 39.0k, RPH = 100k, CT = 470 pF, VCPH = 0.0V, VSD = 0.0V, VCOMP = 0.0V, VCS = 0.0V, CLO = CHO = 1000pF, TA = 25oC unless otherwise specified.
Symbol Definition
Min.
10.0 8.5 1.5 120 -- 14.3
Typ.
11.5 9.5 2.0 170 2.3 15.6
Max.
12.5 10.7 3.0 280 4.0 16.5
Units Test Conditions
VCC rising from 0V V VCC falling from 14V
Supply Characteristics
VCCUV+ VCCUVVUVHYS IQCCUV IQCC VCLAMP VCC supply undervoltage positive going threshold VCC supply undervoltage negative going threshold VCC supply undervoltage lockout hysteresis UVLO mode quiescent current Quiescent VCC supply current VCC zener clamp voltage
A mA V
VCC = 8V CT connected toCOM VCC =14V ICC = 10mA
Floating Supply Characteristics
IQBS0 IQBS1 VBSMIN ILK Quiescent VBS supply current Quiescent VBS supply current Minimum required VBS voltage for proper HO functionality Offset supply leakage current -1 5 -- -- 0 30 2.5 -- 5 60 -- 50 A V A VB = VS = 600V VHO = VS (CT = 0V) VHO = VB (CT = 14V)
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IR2166
Electrical Characteristics cont.
VCC = VBS = VBIAS = 14V +/- 0.25V, VBUS = Open, RT = 39.0k, RPH = 100k, CT = 470 pF, VCPH = 0.0V, VSD = 0.0V, VCOMP = 0.0V, VCS = 0.0V, CLO = CHO = 1000pF, TA = 25oC unless otherwise specified.
Symbol Definition
Min.
5 -50 10.5 --
Typ.
35 -30 13.5 0.25
Max.
55 -18 14.5
Units
Test Conditions
VCPH = 14V VBUS = 3.5V VCPH = 14V VBUS = 4.5V VBUS = 3.0V VBUS = 5.0V
PFC Error Amplifier Characteristics
ICOMP Error amplifier output current sourcing SOURCE ICOMP Error amplifier output current sinking SINK VCOMPOH Error amplifier output voltage swing (high state) VCOMPOL Error amplifier output voltage swing (low state) A
V 4
PFC DC Bus Regulation
VBUSOV VBUSOV HYS VVBUS REG Overvoltage comparator threshold Overvoltage comparator hysterisis VBUS internal reference voltage 3.8 75 3.7 4.3 100 4.0 4.7 300 4.2 V mV V VCOMP = 4.0V VCOMP = 4V VCOMP = 4V
PFC Zero Current Detector
VZX ZX pin comparator threshold voltage VZXhys ZX pin comparator hysterisis VZXclamp ZX pin clamp voltage (high state) 1.1 75 6.3 1.65 300 7.5 2 800 9.1 V mV V VCOMP = 4V VCOMP = 4V IZX = 5mA
PFC Watch-dog
tWD Watch-dog pulse interval 90 400 810
S
ZX = 0V, VCOMP> =2V
Ballast Control Oscillator Characteristics
fosc d VCT+ VCTVCTFLT tDLO tDHO Oscillator frequency Oscillator duty cycle Upper CT ramp voltage threshold Lower CT ramp voltage threshold Fault-mode CT lead voltage LO output deadtime HO output deadtime 38.5 71 -- 6.8 1.8 -- 0.7 0.7 42 75 50 8.4 4.6 0 1.0 1.0 47.5 81 -- 10.7 5.6 -- 1.5 1.5 kHz % V usec VCC = 14V SD > 5.0V or CS >1.3V CT = 470pF Run mode Preheat mode
Ballast Control Preheat Characteristics
I CPH CPH pin charging current VCPHFLT Fault-mode CPH pin voltage 2.6 -- 3.2 0 4.3 -- A mV
VCPH=5V,CT=0V, VBUS=0V
SD > 5.0V or CS >1.3V
RPH Characteristics
I RPHLK Open circuit RPH pin leakage current VRPHFLT Fault-mode RPH pin voltage -- -- 0.1 0 -- -- A mV SD > 5.0V or CS >1.3V
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IR2166
Electrical Characteristics cont.
VCC = VBS = VBIAS = 14V +/- 0.25V, VBUS = Open, RT = 39.0k, RPH = 100k, CT = 470 pF, VCPH = 0.0V, VSD = 0.0V, VCOMP = 0.0V VCS = 0.0V, CLO = CHO = 1000pF, TA = 25oC unless otherwise specified.
Symbol Definition
Min.
-- --
Typ.
0.1 0
Max.
-- --
Units
A mV
Test Conditions
CT = 10V SD > 5.0V or CS >1.3V
RT Characteristics
I RTLK VRTFLT Open circuit RT pin leakage current Fault-mode RT pin voltage
Protection Circuitry Characteristics
V SDTH+ V SDHYS VSDEOL+ VSDEOLV CSTH+ #FAULTVBUSUVV CPH Rising shutdown pin reset threshold voltage Shutdown pin 5.0V threshold hysteresis Rising shutdown pin end-of-life threshold volt. Falling shutdown pin end-of-life threshold volt. Over-current sense threshold voltage Number of sequential over-current fault cycles before IC shuts down The VBUS threshold below which the IC shuts down CPH pin end-of-life enable threshold 4.7 100 2.4 0.7 1.0 25 2.6 10.3 5.2 150 3.0 1.0 1.2 75 3.0 12 5.7 350 3.6 1.6 1.3 90 3.3 V 13.2 V mV V Cycles VCPH>12V VCPH>7.5V VCPH>7.5V, CYCLES CS > 1.3V
Gate Driver Output Characteristics (HO, LO and PFC pins)
VOL VOH tr tf I0+ I0Low-level output voltage High-level output voltage Turn-on rise time Turn-off fall time HO, LO, PFC source current HO, LO, PFC sink current -- -- -- -- -- -- 0 0 110 55 300 400 100 100 210 160 -- -- mV nsec mA Io = 0 VBIAS - Vo, Io = 0 CHO = CLO = CPFC = 1nF
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IR2166
Block Diagram
Vcc 13
S1
RT 3
S2 40K
R Soft Start R Comp 1 T VTH R R Q Q Driver Logic
14
VB
CT 5
RDT 3.0K S3 S4 R
HighSide Driver
16
HO
15
VS
S6
Fault Logic
RPH
4
R 3uA Schmitt 1
Fault Counter LowSide Driver
11
LO
CPH 2 COM 12
S R1 R2 Q Q
Comp 3
10
1.3V 3V UnderVoltage Detect CPH>12V CPH>12V 7.6V 2.0V 1V 1.0M
CS
9
Over-Voltage Protection OTA1
4.3V
SD/EOL
VBUS 1
4.0V
Gain
5.2V
VCC
8
COMP 6
S Under-Voltage Reset S
3.0V VCC
PFC
Q Q Watch Dog Timer
R
Q Q S R1 R2 Q Q
R
ZX 7
1.0V 7.6V
6
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IR2166
State Diagram
Power Turned On
UVLO Mode
Off IQCC 400A CPH = 0V CT = 0V (Oscillator Off)
1/ -Bridge 2
SD/EOL > 5.0V (Lamp Removal) or VCC < 9.5V (UV-) (Power Turned Off)
VCC > 11.5V (UV+) and SD/EOL < 5.0V
VCC < 9.5V (VCC Fault or Power Down) or SD/EOL > 5.0V (Lamp Fault or Lamp Removal)
FAULT Mode
Fault Latch Set 1/ -Bridge Off 2 IQCC 180A CPH = 0V VCC = 15.6V CT = 0V (Oscillator Off) CS > 1.3V for 25 cycles
PREHEAT Mode
/2-Bridge oscillating @ f PH RPH // RT CPH Charging @ ICPH = 5 A PFC Enabled (High Gain) CS Enabled Fault Counter Enabled
1
CPH > 10V (End of PREHEAT Mode)
CS > 1.3V for 25 cycles (Failure to Strike Lamp)
Ignition Ramp Mode
RPH!Open fPH ramps to fRUN CPH charging
CS > 1.3V (Lamp Fault) or SD/EOL<1.0V or SD/EOL>3.0V (End-of-Life)
CPH > 12V
RUN Mode
RPH = Open 1/2-Bridge Oscillating @fRUN EOL Thresholds Enabled PFC = Low Gain Mode VBUS UV Threshold Enabled Fault Counter Disabled VBUS<3.0V Discharge VCC to UVLO-
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IR2166
Lead Assignments & Definitions
VBUS HO
1
CPH
16
VS
Pin # Symbol
1 VBUS CPH RT RPH CT COMP ZX PFC SD/EOL CS LO COM VCC VB VS HO 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Description
DC Bus Sensing Input Preheat Timing Capacitor Minimum Frequency Timing Resistor Preheat Frequency Timing Resistor Oscillator Timing Capacitor PFC Error Amplifier Compensation PFC Zero-Crossing Detection PFC Gate Driver Output Shut-Down/End of Life Sensing Circuit Current Sensing Input Low-Side Gate Driver Output IC Power & Signal Ground Logic & Low-Side Gate Driver Supply High-Side Gate Driver Floating Supply High Voltage Floating Return High-Side Gate Driver Output
2
RT
15
VB
3
RPH
14
IR2166
VCC
4
CT
13
COM
5
COMP
12
LO
6 7
ZX
11
CS
7
PFC
10
SD/EOL
8
9
8
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IR2166
BALLAST TIMING DIAGRAMS NORMAL OPERATION
VCC
15.6V UVLO+ UVLO-
VCC 7.5V
CPH
frun
FREQ
fph
HO LO CS
1.3V
Over-Current Threshold
IGN
UVLO
PH
RUN
UVLO
RT
RT
RT
RPH
RPH
RPH
CT
CT
CT
HO
HO
HO
LO
LO
LO
CS
CS
CS
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IR2166
BALLAST TIMING DIAGRAMS
VCC
15.6V UVLO+ UVLO-
FAULT CONDITION
VCC 7.5V
CPH
f run
FREQ
fp
h
SD
HO LO CS
1.3V
SD > 5.1V
FAULT
IGN
IGN
UVLO
PH
PH
RUN
UVLO
RT
RT
RT
RPH CT
RPH
RPH CT
CT
HO
HO LO
HO LO
LO
CS
CS
CS
10
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IR2166
14 12 10
VCC (V)
1600
UVLO+ UVLOCT (pF)
1400 1200 1000 800 600
8 6 4
400
2 0 -25 0 25 50 75 100 125 Temperature (C)
200 0 0 0.5 1 1.5 DeadTime(S) 2 2.5 3
Graph 1. VCCUV+, VCCUV- vs TEMP
Graph 2. CT vs Dead Time
9 8 7 6
1000000
CT+ CTFrequency (KHz) 100000
CT (V)
5 4 3 2 1 0 -25 0 25 50 75 100 125 Temperature (C)
10000
1000 5 25 45 RT(K ) 65 85
Graph 3: CT+, CT- vs TEMP
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Graph 4: Frequency vs RT
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IR2166
8 7 6
3.5 3 2.5 2 ICPH (mA)
5 ICC (mA) 4 3 2 1 0 40 80 120 FREQUENCY (KHz) 160 200
1.5 1 0.5 0 -0.5 -1 -1.5 0 3 6 9 12 15 VCPH (V)
Graph 5: ICC vs Frequency
Graph 6: ICPH vs VCPH
50
2.5
ZX+
ZX Threshold & HYS.(V)
40
2
ILK ( A)
30
1.5
ZX1
20
HYS
0.5
10
0 -25 0 25 50 75 100 125 Temperature (C)
0 -25 0 25 50 75 100 125 Temperature (C)
Graph 7. ILK vs TEMP
12
Graph 8: ZX+, ZX- vs TEMP
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IR2166
325
9
315 IZX(ZXInput Bias) ( A)
8.5
8
305
7.5
295
7
285
6.5
275 -25 0 25 50 75 100 125 Temperature (C)
6 -25 0 25 50 75 100 125 Temperature (C)
Graph 9: IZX (ZX Input Bias) vs TEMP
Graph 10: VZX (ZX Clamp Voltage) vs TEMP
5
5
4.5
4.5 VBUS+
4
4
VBUS-
3.5
3.5
3 -25 0 25 50 75 100 125 Temperature (C)
3 -25 0 25 50 75 100 125 Temperature (C)
Graph 11: VBUS Sense Thresh vs TEMP
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Graph 12: VBUS+, VBUS- vs TEMP
13
IR2166
150
63
125 PFC Trise, Tfall (nS)
Trise
61
100
FREQ(KHz)
100 125
59
75
Tfall
57
50
25
55
0 -25 0 25 50 75 Temperature (C)
53 -25 0 25 50 75 100 125 Temperature (C)
Graph 13: PFC Trise, Tfall vs TEMP
Graph 14: Frequency vs TEMP
2.5
200 175
2.3
150
2.1
t DEAD HO t DEAD LO
t RISE, t FALL (nS)
S)
125 100 75 50 25
tDEAD (
t RISE
1.9
1.7
t FALL
-25 0 25 50 75 100 125
1.5 -25 0 25 50 75 100 125 Temperature (C)
0 Temperature (C)
Graph 15: tDEAD HO, tDEAD LO vs TEMP
14
Graph 16: tRISE, tFALL vs TEMP
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IR2166
50
5
40
CS Threshold (V)
4
# CS Pulses
30
3
20
2
10
1
0 -25 0 25 50 75 100 125 Temperature (C)
0 -25 0 25 50 75 100 125 Temperature (C)
Graph 17: CS Pulses vs TEMP
Graph 18: CS Threshold vs TEMP
3.5
6
EOL+
3 2.5 VSD/EOL (V) 2 1.5 VSD/EOL (V) 5.5
SD+
5
SD-
EOL1 0.5 0 -25 0 25 50 75 100 125 Tem perature (C) 4 -25 0 25 50 75 100 125 Tem perature (C) 4.5
Graph 19: EOL+,EOL- vs TEMP
Graph 20: SD+, SD- vs TEMP
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IR2166
15
3
VCPH(EOL/RUN) Threshold (V)
14
2.5
2 IQCC (mA) -25 0 25 50 75 100 125 13
1.5
12
1 11
0.5
10 Temperature (C)
0 8 9 10 11 12 13 V CC (V)
Graph 21: VCPH (EOL/RUN) Threshold vs TEMP
16 14 12 VCOMP (V) 10 8 6 4
IQBS ( A)
Graph 22: IQCC vs VCC UVLO Hysteresis
90 80 70 60 50 40 30 20 10
2 0 0 5 10 PFC ON TIME (S) 15 20
0 -10 0 3 6 V BS (V ) 9 12 15
Graph 23: VCOMP vs PFC ON TIME
Graph 24: IQBS(1) vs VCC vs Temp
16
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IR2166
20
20 -25 25
16
-25 25 75 125 IQCC (mA)
16
75 125
IQCC (mA)
12
12
8
8
4
4
0 0 5 10 VCC (V) 15 20
0 15 15.5 V CC (V) 16 16.5
Graph 25. IQCC vs VCC vs Temp
Graph 26. IQCC vs V CC vs Temp Internal Zener Diode Curve
2.5
0.3 0.25 0.2 IQCC (mA) 0.15 -25 25 75 125
-2 5
2
25 75 125
1.5
1
0.1 0.05 0 0 3 6 VCC (V) 9 12 15
0.5
0 10 10.5 11 11.5 V C C (V ) 12 12.5 13
Graph 27. IQCC vs VCC vs Temp Micropower Startup Mode
Graph 28: IQCC vs VCC vs Temp VCCUV+
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IR2166
3 2.5
-25 25 75 125
2 IQCC ( A) 1.5 1
0.5 0 8.5 9 9.5 V CC (V) 10 10.5
Graph 29: IQCC vs VCC vs Temp VCCUV-
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IR2166
I. Ballast Section Functional Description
Under-voltage Lock-Out Mode (UVLO) The under-voltage lock-out mode (UVLO) is defined as the state the IC is in when VCC is below the turn-on threshold of the IC. To identify the different modes of the IC, refer to the State Diagram shown on page 7 of this document. The IR2166 undervoltage lock-out is designed to maintain an ultra low supply current of less than 400uA, and to guarantee the IC is fully functional before the high and low side output drivers are activated. Figure 1 shows an efficient supply voltage using the start-up current of the IR2166 together with a charge pump from the ballast output stage (RSUPPLY, CVCC, DCP1 and DCP2).
VBUS(+) R SUPPLY D BOOT HO 16 VS 15 14 VB VCC COM LO 11 M2 D CP1 RCS D CP2 C BOOT C SNUB C VCC M1 Half-Bridge Output
VC1
CVCC DISCHARGE VUVLO+
VHYST INTERNAL VCC ZENER CLAMP VOLTAGE
VUVLO-
DISCHARGE TIME
CHARGE PUMP OUTPUT RSUPPLY & CVCC TIME CONSTANT
t
Figure 2, Supply capacitor (CVCC) voltage.
IR2166
13 12
VBUS(-)
Figure 1, Start-up and supply circuitry.
The start-up capacitor (CVCC) is charged by current through supply resistor (RSUPPLY) minus the start-up current drawn by the IC. This resistor is chosen to set the line input voltage turn-on threshold for the ballast . Once the capacitor voltage on VCC reaches the start-up threshold, and the SD pin is below 5.0 volts, the IC turns on and HO and LO begin to oscillate. The capacitor begins to discharge due to the increase in IC operating current (Figure 2).
During the discharge cycle, the rectified current from the charge pump charges the capacitor above the IC turnoff threshold. The charge pump and the internal 15.6V zener clamp of the IC take over as the supply voltage. The start-up capacitor and snubber capacitor must be selected such that enough supply current is available over all ballast operating conditions. A bootstrap diode (DBOOT) and supply capacitor (CBOOT) comprise the supply voltage for the high side driver circuitry. To guarantee that the high-side supply is charged up before the first pulse on pin HO, the first pulse from the output drivers comes from the LO pin. During under-voltage lockout mode, the highand low-side driver outputs HO and LO are both low, pin CT is connected internally to COM to disable the oscillator, and pin CPH is connected internally to COM for resetting the preheat time. Preheat Mode (PH) The preheat mode is defined as the state the IC is in when the lamp filaments are being heated to their correct emission temperature. This is necessary for maximizing lamp life and reducing the required ignition voltage. The IR2166 enters preheat mode when VCC exceeds the UVLO positive-going threshold. HO and LO begin to
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IR2166
oscillate at the preheat frequency with 50% duty cycle and with a dead-time which is set by the value of the external timing capacitor, CT, and internal deadtime resistor, RDT. Pin CPH is disconnected from COM and an internal 3A current source (Figure 3)
V BUS (+)
RT
3 RT S4
HO OSC. HalfBridge Driver
16
M1
RPH
4 R PH
VS
15
HalfBridge Output ILOAD
CT
5 CT
LO
11
M2
3uA
CPH
2 C CPH
RCS
COM
12
IR2166
Load Return
V BUS (-)
VCC is the dead-time (both off) of the output gate drivers, HO and LO. The selected value of CT together with RDT therefore program the desired dead-time (see Design Equations, page 26, Equations 1 and 2). Once CT discharges below 1/3 VCC, MOSFET S3 is turned off, disconnecting RDT from COM, and MOSFET S1 is turned on, connecting RT and RPH again to VCC. The frequency remains at the preheat frequency until the voltage on pin CPH exceeds 10V and the IC enters Ignition Mode. During the preheat mode, the over-current protection together with the fault counter are enabled. The peak ignition current must not exceed the maximum allowable current ratings of the output stage MOSFETs. Should this voltage exceed the internal threshold of 1.3V, the internal FAULT Counter begins counting the sequential overcurrent faults (See Timing Diagram). If the number of over-current faults exceed 25, the IC will enter FAULT mode and gate driver outputs HO, LO and PFC will be latched low.
Figure 3, Preheat circuitry.
charges the external preheat timing capacitor on CPH linearly. The over-current protection on pin CS is disabled during preheat. The preheat frequency is determined by the parallel combination of resistors RT and RPH, together with timing capacitor CT. CT charges and discharges between 1/3 and 3/5 of VCC (see Timing Diagram, page 9). CT is charged exponentially through the parallel combination of RT and RPH connected internally to VCC through MOSFET S1. The charge time of CT from 1/3 to 3/5 VCC is the on-time of the respective output gate driver, HO or LO. Once CT exceeds 3/5 VCC, MOSFET S1 is turned off, disconnecting RT and RPH from VCC. CT is then discharged exponentially through an internal resistor, RDT, through MOSFET S3 to COM. The discharge time of CT from 3/5 to 1/3
20
V BUS (+) VCC
13
S1
RT
3 RT
S4
HO OSC HalfBridge Driver Fault Logic LO
11
S3
1.3V
16
M1
RPH
4 R PH
VS
15
HalfBridge Output I LOAD
CT
5 CT
M2
CS
10
R1 CCS
3uA
CPH
2 CCPH
Comp 4
RCS
12
COM Load Return
IR2166
V BUS (-)
Figure 4, Ignition circuitry.
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IR2166
Ignition Mode (IGN) The ignition mode is defined as the state the IC is in when a high voltage is being established across the lamp necessary for igniting the lamp. The IR2166 enters ignition mode when the voltage on pin CPH exceeds 10V. Pin CPH is connected internally to the gate of a P-channel MOSFET (S4) (see Figure 4) that connects pin RPH with pin RT. As pin CPH exceeds 10V, the gate-to-source voltage of MOSFET S4 begins to fall below the turn-on threshold of S4. As pin CPH continues to ramp towards VCC, switch S4 turns off slowly. This results in resistor RPH being disconnected smoothly from resistor RT, which causes the operating frequency to ramp smoothly from the preheat frequency, through the ignition frequency, to the final run frequency. The over-current threshold on pin CS will protect the ballast against a non-strike or open-filament lamp fault condition. The voltage on pin CS is defined by the lower half-bridge MOSFET current flowing through the external current sensing resistor RCS. The resistor RCS therefore programs the maximum allowable peak ignition current (and therefore peak ignition voltage) of the ballast output stage. If the number of over current pulses exceed 25, the IC will enter fault mode and gate driver outputs HO, LO and PFC will be latched low. Run Mode (RUN) Once the lamp has successfully ignited, the ballast enters run mode. The run mode is defined as the state the IC is in when the lamp arc is established and the lamp is being driven to a given power level. The run mode oscillating frequency is determined by the timing resistor
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RT and timing capacitor CT (see Design Equations, page 26, Equations 3 and 4). Should hard-switching occur at the half-bridge at any time due to an open-filament or lamp removal, the voltage across the current sensing resistor, RCS, will exceed the internal threshold of 1.3 volts and the IC will enter FAULT mode and gate driver outputs HO, LO and PFC will be latched low. DC Bus Under-voltage Reset Should the DC bus decrease too low during a brownout line condition or overload condition, the resonant output stage to the lamp can shift near or below resonance. This can produce hard-switching at the half-bridge which can damage the half-bridge switches or, the DC bus can decrease too far and the lamp can extinguish. To protect against this, the VBUS pin includes a 3.0V under-voltage threshold. Should the voltage at the VBUS pin decrease below 3.0V, VCC will be discharged to the UVLO- threshold and all gate driver outputs will be latched low. For proper ballast design, the designer should design the PFC section such that the DC bus does not drop until the AC line input voltage falls below the rated input voltage of the ballast (See PFC section). When correctly designed, the voltage measured at the VBUS pin will decrease below the internal 3.0V threshold and the ballast will turn off cleanly. The pull-up resistor to VCC (RSUPPLY) will then turn the ballast on again with the AC input line voltage increasing to the minimum specified value causing VCC to exceed UVLO+. RSUPPLY should be set to turn the ballast on at the minimum specified ballast input voltage. The PFC should then be designed such that the DC bus decreases at an input line voltage that is
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IR2166
lower than the minimum specified ballast input voltage. This hysteresis will result in clean turnon and turnoff of the ballast. CS and EOL Fault Mode (FAULT) Should the voltage at the SD/EOL pin exceed 3V or decrease below 1V during RUN mode, the IC enters fault mode and all gate driver outputs, HO, LO and PFC, are latched off in the 'low' state. CPH is discharged to COM for resetting the preheat time, and CT is discharged to COM for disabling the oscillator. To exit fault mode, VCC must be recycled back below the UVLO negativegoing turn-off threshold, or, the shutdown pin, SD, must be pulled above 5.2 volts. Either of these will force the IC to enter UVLO mode (see State Diagram, page 7). Once VCC is above the turnon threshold and SD is below 5.0 volts, the IC will begin oscillating again in the preheat mode. The current sense function will force the IC to enter FAULT mode only after the voltage at the current sense pin has been pulsed about 25 times with a voltage greater than 1.3 volts during preheat and ignition modes only. These over-currents must occur during the on-time of LO. During run mode, a single pulse on the CS pin above 1.3V will force the IC to enter FAULT mode.
25 Pulses LO
II. PFC Section Functional Description
In most electronic ballasts it is necessary to have the circuit act as a pure resistive load to the AC input line voltage. The degree to which the circuit matches a pure resistor is measured by the phase shift between the input voltage and input current and how well the shape of the input current waveform matches the shape of the sinusoidal input voltage. The cosine of the phase angle between the input voltage and input current is defined as the power factor (PF), and how well the shape of the input current waveform matches the shape of the input voltage is determined by the total harmonic distortion (THD). A power factor of 1.0 (maximum) corresponds to zero phase shift and a THD of 0% represents a pure sinewave (no distortion). For this reason it is desirable to have a high PF and a low THD. To achieve this, the IR2166 includes an active power factor correction (PFC) circuit which, for an AC line input voltage, produces an AC line input current. The control method implemented in the IR2166 is for a boosttype converter (Figure 6) running in criticalconduction mode (CCM). This means that during each switching cycle of the PFC MOSFET, the circuit waits until the inductor current discharges to zero before turning the PFC MOSFET on again. The PFC MOSFET is turned on and off at a much higher frequency (>10KHz) than the line input frequency (50 to 60Hz).
LPFC (+) DPFC DC Bus
CS
2.0V
+ MPFC (-)
Fault Mode
CBUS
Run Mode
Figure 5: FAULT counter during preheat and ignition
Figure 6: Boost-type PFC circuit
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IR2166
When the switch MPFC is turned on, the inductor LPFC is connected between the rectified line input (+) and (-) causing the current in LPFC to charge up linearly. When MPFC is turned off, LPFC is connected between the rectified line input (+) and the DC bus capacitor CBUS (through diode DPFC) and the stored current in LPFC flows into CBUS. As MPFC is turned on and off at a high-frequency, the voltage on CBUS charges up to a specified voltage. The feedback loop of the IR2166 regulates this voltage to a fixed value by continuously monitoring the DC voltage and adjusting the on-time of MPFC accordingly. For an increasing DC bus the ontime is decreased, and for a decreasing DC bus the on-time is increased. This negative feedback control is performed with a slow loop speed and a low loop gain such that the average inductor current smoothly follows the low-frequency line input voltage for high power factor and low THD. The on-time of MPFC therefore appears to be fixed (with an additional modulation to be discussed later) over several cycles of the line voltage. With a fixed on-time, and an off-time determined by the inductor current discharging to zero, the result is a system where the switching frequency is free-running and constantly changing from a high frequency near the zero crossing of the AC input line voltage, to a lower frequency at the peaks (Figure 7).
V, I
t
Figure 7: Sinusoidal line input voltage (solid line), triangular PFC Inductor current and smoothed sinusoidal line input current (dashed line) over one half-cycle of the line input voltage.
When the line input voltage is low (near the zero crossing), the inductor current will charge up to a small amount and the discharge time will be fast resulting in a high switching frequency. When the input line voltage is high (near the peak), the inductor current will charge up to a higher amount and the discharge time will be longer giving a lower switching frequency. The triangular PFC inductor current is then smoothed by the EMI filter to produce a sinusoidal line input current. The PFC control circuit of the IR2166 (Figure 8) only requires four control pins: VBUS, COMP, ZX and PFC. The VBUS pin is for sensing the DC bus voltage (via an external resistor voltage divider), the COMP pin programs the on-time of MPFC and the speed of the feedback loop, the ZX pin detects when the inductor current discharges to zero (via a secondary winding from the PFC inductor), and the PFC pin is the low-side gate driver output for MPFC.
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IR2166
LPFC
(+)
DFPC Run Mode Signal
Fault Mode Signal
VBUS 1
GAIN 4.0V OTA1 4.3V RS3 COMP4 VCC
8
PFC
COMP 6
RVBUS1 RZX
COMP2 Discharge VCC to UVLOM1
COMP5 S R Q Q WATCH DOG TIMER RS4 SQ R1 R2 Q
VBUS
ZX
3.0V
C1 M2
COMP
PFC Control
CBUS PFC RPFC MPFC
ZX 7
7.6V 2.0V
COMP3
COM DCOMP CCOMP RVBUS
Figure 9: IR2166 detailed PFC control circuit
(-)
Figure 8:IR2166 simplified PFC control circuit
The VBUS pin is regulated against a fixed internal 4V reference voltage for regulating the DC bus voltage (Figure 9). The feedback loop is performed by an operational transconductance amplifier (OTA) that sinks or sources a current to the external capacitor at the COMP pin. The resulting voltage on the COMP pin sets the threshold for the charging of the internal timing capacitor (C1) and therefore programs the ontime of MPFC. During preheat and ignition modes of the ballast section, the gain of the OTA is set to a high level to raise the DC bus level quickly. When the voltage on the VBUS pin exceeds 3V, the gain is set to a low level to reduce overshoot. When the voltage on the VBUS pin exceeds 4V, the gain is set to a high level again to minimize the transient on the DC bus which can occur during ignition. During run mode, the gain is then decreased to a lower level necessary for achieving high power factor and low THD.
The off-time of MPFC is determined by the time it takes the LPFC current to discharge to zero. This zero current level is detected by a secondary winding on LPFC which is connected to the ZX pin. A positive-going edge exceeding the internal 2V threshold signals the beginning of the off-time. A negative-going edge on the ZX pin falling below 1.7V will occur when the LPFC current discharges to zero which signals the end of the off-time and MPFC is turned on again (Figure 10). The cycle repeats itself indefinitely until the PFC section is disabled due to a fault detected by the ballast section (Fault Mode), an over-voltage or under-voltage condition on the DC bus, or, the negative transition of ZX pin voltage does not occur. Should the negative edge on the ZX pin not occur, MPFC will remain off until the watch-dog timer forces a turn-on of MPFC for an on-time duration programmed by the voltage on the COMP pin. The watch-dog pulses occur every 400s indefinitely until a correct positive- and negativegoing signal is detected on the ZX pin and normal PFC operation is resumed.
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IR2166
ILPFC
0
modulation circuit has been added to the PFC control. This circuit dynamically increases the on-time of MPFC as the line input voltage nears the zero-crossings (Figure 11). This causes the peak LPFC current, and therefore the smoothed line input current, to increase slightly higher near the zero-crossings of the line input voltage. This reduces the amount of cross-over distortion in the line input current which reduces the THD and higher harmonics to low levels.
PFC pin
0
ILPFC
0
ZX pin
0
PFC pin
0
near peak region of rectified AC line
near zero-crossing region of rectified AC line
Figure 10: LPFC current, PFC pin and ZX pin timing diagram.
Figure 11: On-time modulation near the zero-crossings.
On-time Modulation A fixed on-time of MPFC over an entire cycle of the line input voltage produces a peak inductor current which naturally follows the sinusoidal shape of the line input voltage. The smoothed averaged line input current is in phase with the line input voltage for high power factor but the total harmonic distortion (THD), as well as the individual higher harmonics, of the current can still be too high. This is mostly due to crossover distortion of the line current near the zerocrossings of the line input voltage. To achieve low harmonics which are acceptable to international standard organizations and general market requirements, an additional on-time
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Over-voltage Protection (OVP) Should over-voltage occur on the DC bus causing the VBUS pin to exceed the internal 4.3V threshold, the PFC output is disabled (set to a logic 'low'). When the DC bus decreases again causing the VBUS pin to decrease below the internal 4V threshold, a watch-dog pulse is forced on the PFC pin and normal PFC operation is resumed. Under-voltage Reset (UVR) When the line input voltage is decreased, interrupted or a brown-out condition occurs, the PFC feedback loop causes the on-time of MPFC
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IR2166
to increase in order to keep the DC bus constant. Should the on-time increase too far, the resulting peak currents in LPFC can exceed the saturation current limit of LPFC. LPFC will then saturate and very high peak currents and di/dt levels will occur. To prevent this, the maximum on-time is limited by limiting the maximum voltage on the COMP pin with an external zener diode DCOMP (Figure 8). As the line input voltage decreases, the COMP pin voltage and therefore the on-time will eventually limit. The PFC can no longer supply enough current to keep the DC bus fixed for the given load power and the DC bus will begin to drop. Decreasing the line input voltage further will cause the VBUS pin to eventually decrease below the internal 3V threshold (Figure 9). When this occurs, VCC is discharged internally to UVLO-, the IR2166 enters UVLO mode and both the PFC and ballast sections are disabled (see State Diagram). The start-up supply resistor to VCC, together with the micropower start-up current of the IR2166, determine the line input turn-on voltage. This should be set such that the ballast turns on at a line voltage level above the under-voltage turn-off level. It is the correct selection of the value of the supply resistor to VCC and the zener diode on the COMP pin that correctly program the on and off line input voltage thresholds for the ballast. With these thresholds correctly set, the ballast will turn off due to the 3V under-voltage threshold on the VBUS pin, and on again at a higher line input voltage (hysterisis) due to the supply resistor to VCC. This hysterisis will result in a proper reset of the ballast without flickering of the lamp, bouncing of the DC bus or re-ignition of the lamp when the DC bus is too low.
Ballast Design Equations Note: The results from the following design equations can differ slightly from experimental measurements due to IC tolerances, component tolerances, and oscillator over- and undershoot due to internal comparator response time. Step 1: Program Dead-time The dead-time between the gate driver outputs HO and LO is programmed with timing capacitor CT and an internal dead-time resistor RDT. The dead-time is the discharge time of capacitor CT from 3/5VCC to 1/3VCC and is given as:
t DT = CT 1475 [Seconds]
or
(1)
CT =
t DT 1475
[Farads]
(2)
Step 2: Program Run Frequency The final run frequency is programmed with timing resistor RT and timing capacitor CT. The charge time of capacitor CT from 1/3VCC to 3/5VCC determines the on-time of HO and LO gate driver outputs. The run frequency is therefore given as:
f RUN =
or
1 2 C T (0.51 RT + 1475)
[Hertz] (3)
RT =
1 - 2892 1.02 C T f RUN
[Ohms] (4)
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IR2166
Step 3: Program Preheat Frequency The preheat frequency is programmed with timing resistors RT and RPH, and timing capacitor CT. The timing resistors are connected in parallel internally for the duration of the preheat time. The preheat frequency is therefore given as:
f PH = 1 0.51 RT R PH 2 CT + 1475 [Hertz] (5) R +R T PH
Step 5: Program Maximum Ignition Current The maximum ignition current is programmed with the external resistor RCS and an internal threshold of 1.3 volts. This threshold determines the over-current limit of the ballast, which can be exceeded when the frequency ramps down towards resonance during ignition and the lamp does not ignite. The maximum ignition current is given as:
I IGN =
or
1 .3 RCS
[Amps Peak] (9)
or
1 1.02 C f - 2892 RT T PH = 1 RT - 1.02 C f - 2892 T PH
R PH
RCS =
[Ohms] (6)
1.3 I IGN
[Ohms] (10)
Step 4: Program Preheat Time The preheat time is defined by the time it takes for the capacitor on pin CPH to charge up to 10 volts. An internal current source of 3uA flows out of pin CPH. The preheat time is therefore given as:
t PH = CPH 3.33e6
[Seconds] (7)
or
C PH = t PH 0 . 3 e - 6
[Farads] (8)
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IR2166
P F C D e s ig n E q u a tio n s
S te p 1 : C a lc u la te P F C in d u c to r v a lu e :
L PFC =
w h e re ,
(VBUS - 2 VAC MIN ) VAC 2 f MIN POUT VBUS
2 MIN
[H e n rie s] (1 )
VBUS VAC MIN
f MIN POUT
= = = = =
D C b u s v o lta g e M in im u m rm s A C in p u t v o lta g e P F C e ffic ie n c y (ty p ic a lly 0 .9 5 ) M in im u m P F C s w itc h in g fre q u e n c y a t m in im u m A C in p u t v o lta g e B a lla s t o u tp u t p o w e r
S te p 2 : C a lc u la te p e a k P F C in d u c to r c u rre n t:
i PK =
2 2 POUT VAC MIN i PK
[A m p s P e a k ]
(2 )
N o te : T h e P F C in d u c to r m u s t n o t s a tu ra te a t
o v e r th e s p e c ifie d b a lla s t o p e ra tin g te m p e ra tu re ra n g e .
P ro p e r c o re s iz in g a n d a ir-g a p p in g s h o u ld b e c o n s id e re d in th e in d u c to r d e s ig n .
S te p 3 : C a lc u la te m a x im u m o n -tim e :
t ON MAX =
2 POUT L PFC 2 VAC MIN
[S e c o n d s]
(3 )
S te p 4 : C a lc u la te m a x im u m C O M P v o lta g e :
V COMP
MAX
=
t ON MAX 0 .9 E - 6
[V o lts]
(4 )
S te p 5 : S e le c t z e n e r d io d e D C O M P v a lu e :
D COMP z e n e r v o lta g e V COMP
S te p 6 : C a lc u la te re s is to r R S U P P L Y v a lu e :
MAX
[V o lts] (5 )
R SUPPLY
=
VAC
MIN
PK
+ 10
[O h m s] (6 )
IQCCUV
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IR2166
Case outline
16 Lead PDIP
01-6015 01-3065 00 (MS-001A)
16 Lead SOIC (narrow body)
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01-6018 01-3064 00 (MS-012AC)
http://www.irf.com/ Data and specifications subject to change without notice.
3/19/2003
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